120 lines
3.2 KiB
C
120 lines
3.2 KiB
C
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/* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef _UART_H_
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#define _UART_H_
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#include "cpr_types.h"
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/*
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* Telecaster specific defines
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*/
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#define SYSCLOCK ((unsigned long)25000000) /* 25 MHZ */
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#define UART_BASE_ADDRESS (UART_16550_REGS *)0xFFFE4000
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/*
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* 16550 register definition
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*/
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typedef struct {
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volatile uint8_t dc; /* RBR/THR */
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volatile uint8_t ier; /* Interrupt Enable Reg */
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volatile uint8_t iir; /* Interrupt ID Reg */
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volatile uint8_t lcr; /* Line Control Reg / FIFO Control Reg */
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volatile uint8_t mcr; /* Modem Control Register */
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volatile uint8_t lsr; /* Line Status Register */
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volatile uint8_t msr; /* Modem Status Register */
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volatile uint8_t scr; /* Scratch Register */
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} UART_16550_REGS;
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/*
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* UART register bit symbols
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*/
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#define UART_IER_MASK 0xF0
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#define IER_RX_IE 0x01
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#define IER_TX_IE 0x02
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#define IER_LS_IE 0x04
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#define IER_MS_IE 0x08
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#define UART_IIR_RV 0x01
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#define IIR_IPEND 0x01
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#define IIR_MODEM_STAT 0x00
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#define IIR_TX_EMPTY 0x02
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#define IIR_RX_AVAIL 0x04
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#define IIR_RX_LINE_STAT 0x06
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#define IIR_CHAR_TIMOUT 0x0C
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#define UART_FCR_MASK 0x30
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#define FCR_FIFO_EN 0x01
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#define FCR_CLR_RXF 0x02
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#define FCR_CLR_TXF 0x04
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#define FCR_TRIGR_1BYT 0x00
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#define FCR_TRIGR_4BYT 0x40
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#define FCR_TRIGR_8BYT 0x80
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#define FCR_TRIGR_14BYT 0xC0
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#define LCR_CHR_LEN_5BIT 0x00
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#define LCR_CHR_LEN_6BIT 0x01
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#define LCR_CHR_LEN_7BIT 0x02
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#define LCR_CHR_LEN_8BIT 0x03
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#define LCR_STOP1 0x00
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#define LCR_STOP2 0x04
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#define LCR_PAR_EN 0x08
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#define LCR_PAR_ODD 0x10
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#define LCR_FIX_PAR 0x20
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#define LCR_BRK_CTL 0x40
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#define LCR_DLAB 0x80
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#define MCR_DTR 0x01
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#define MCR_RTS 0x02
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#define MCR_OUT1 0x04
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#define MCR_OUT2 0x08
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#define MCR_LPBK 0x10
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#define MCR_AUTO_FLW_EN 0x20
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#define UART_LSR_RV 0x60
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#define LSR_RX_AVAIL 0x01
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#define LSR_OVRUN 0x02
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#define LSR_PAR_ERR 0x04
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#define LSR_FRAM_ERR 0x08
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#define LSR_BRK_INT 0x10
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#define LSR_TX_EMPTY 0x20
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#define LSR_XMITR_EMPTY 0x40
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#define LSR_RX_FIFO_ERR 0x80
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#define UART_MSR_RV 0x00
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#define MSR_CTS_CHG 0x01
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#define MSR_DSR_CHG 0x02
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#define MSR_TERI 0x04
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#define MSR_CD_CHG 0x08
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#define MSR_CTS_IN 0x10
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#define MSR_DSR_IN 0x20
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#define MSR_RI_IN 0x40
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#define MSR_CD_IN 0x80
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#define DATAREADY 0x01
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#define XMITFIFOEMPTY 0x20
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#define RXLINESTATUS (3<<1)
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#define RXDATAAVAIL (2<<1)
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#define CHARTIMEOUT (6<<1)
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#define TXEMPTY (1<<1)
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#define MODEMSTATUS (0<<1)
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#define RXERRORS 0x8E
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#define DATAREADY 0x01
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#define XMITFIFOEMPTY 0x20
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#define TX_EMPTY 0x01
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//extern int uart_init(int speed, char *buf, int buf_size);
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extern int32_t uart_init();
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extern void uart_flush(int32_t dev);
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extern int32_t uart_outc(int8_t c, void *);
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extern int32_t uart_outs(int8_t *s, void *);
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#endif
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