mirror of
https://github.com/signalwire/freeswitch.git
synced 2025-02-05 02:34:18 +00:00
d2edcad66e
Thanks to Phil Zimmermann for the code and for the license exception we needed to include it. There remains some build system integration work to be done before this code will build properly in the FreeSWITCH tree.
415 lines
9.1 KiB
NASM
415 lines
9.1 KiB
NASM
;;; Copyright (c) 1995, Colin Plumb.
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;;; For licensing and other legal details, see the file legal.c.
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;;;
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;;; Assembly primitives for bignum library, 80386 family, 32-bit code.
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;;;
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;;; Several primitives are included here. Only lbnMulAdd1 is *really*
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;;; critical, but once that's written, lnmMulN1 and lbnMulSub1 are quite
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;;; easy to write as well, so they are included here as well.
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;;; lbnDiv21 and lbnModQ are so easy to write that they're included, too.
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;;;
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;;; All functions here are for 32-bit flat mode. I.e. near code and
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;;; near data, although the near offsets are 32 bits.
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;;;
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;;; The usual 80x86 calling conventions have AX, BX, CX and DX
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;;; volatile, and SI, DI, SP and BP preserved across calls.
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;;; This includes the "E"xtended forms of all of those registers
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;;;
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;;; However, just to be confusing, recent 32-bit DOS compilers have
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;;; quietly changed that to require EBX preserved across calls, too.
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;;; Joy.
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.386
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;_TEXT segment para public use32 'CODE' ; 16-byte aligned because 486 cares
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;_TEXT ends
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ifdef @Version
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if @Version le 510
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FLAT group _TEXT
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endif
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else
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FLAT group _TEXT
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endif
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assume cs:FLAT, ds:FLAT, ss:FLAT
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_TEXT segment para public use32 'CODE' ; 16-byte aligned because 486 cares
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public _lbnMulN1_32
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public _lbnMulAdd1_32
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public _lbnMulSub1_32
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public _lbnDiv21_32
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public _lbnModQ_32
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;; Register usage:
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;; eax - low half of product
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;; ebx - carry to next iteration
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;; ecx - multiplier (k)
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;; edx - high half of product
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;; esi - source pointer
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;; edi - dest pointer
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;; ebp - loop counter
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;;
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;; Stack frame:
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;; +--------+ esp+20 esp+24 esp+28 esp+32 esp+36
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;; | k |
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;; +--------+ esp+16 esp+20 esp+24 esp+28 esp+32
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;; | len |
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;; +--------+ esp+12 esp+16 esp+20 esp+24 esp+28
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;; | in |
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;; +--------+ esp+8 esp+12 esp+16 esp+20 esp+24
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;; | out |
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;; +--------+ esp+4 esp+8 esp+12 esp+16 esp+20
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;; | return |
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;; +--------+ esp esp+4 esp+8 esp+12 esp+16
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;; | esi |
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;; +--------+ esp esp+4 esp+8 esp+12
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;; | ebp |
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;; +--------+ esp esp+4 esp+8
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;; | ebx |
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;; +--------+ esp esp+4
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;; | edi |
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;; +--------+ esp
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align 16
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_lbnMulN1_32 proc near
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push esi ; U
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mov esi,[esp+12] ; V load in
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push ebp ; U
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mov ebp,[esp+20] ; V load len
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push ebx ; U
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mov ecx,[esp+28] ; V load k
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push edi ; U
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mov edi,[esp+20] ; V load out
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;; First multiply step has no carry in.
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mov eax,[esi] ; U
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lea ebx,[ebp*4-4] ; V loop unrolling
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mul ecx ; NP first multiply
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mov [edi],eax ; U
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and ebx,12 ; V loop unrolling
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add esi,ebx ; U loop unrolling
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add edi,ebx ; V loop unrolling
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jmp DWORD PTR m32_jumptable[ebx] ; NP loop unrolling
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align 4
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m32_jumptable:
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dd m32_case0
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dd m32_case1
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dd m32_case2
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dd m32_case3
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nop
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align 8
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nop
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nop
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nop ; Get loop nicely aligned
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m32_case0:
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sub ebp,4 ; U
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jbe SHORT m32_done ; V
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m32_loop:
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mov eax,[esi+4] ; U
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mov ebx,edx ; V Remember carry for later
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add esi,16 ; U
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add edi,16 ; V
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mul ecx ; NP
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add eax,ebx ; U Add carry in from previous word
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adc edx,0 ; U
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mov [edi-12],eax ; V
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m32_case3:
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mov eax,[esi-8] ; U
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mov ebx,edx ; V Remember carry for later
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mul ecx ; NP
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add eax,ebx ; U Add carry in from previous word
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adc edx,0 ; U
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mov [edi-8],eax ; V
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m32_case2:
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mov eax,[esi-4] ; U
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mov ebx,edx ; V Remember carry for later
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mul ecx ; NP
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add eax,ebx ; U Add carry in from previous word
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adc edx,0 ; U
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mov [edi-4],eax ; V
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m32_case1:
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mov eax,[esi] ; U
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mov ebx,edx ; V Remember carry for later
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mul ecx ; NP
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add eax,ebx ; U Add carry in from previous word
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adc edx,0 ; U
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mov [edi],eax ; V
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sub ebp,4 ; U
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ja SHORT m32_loop ; V
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m32_done:
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mov [edi+4],edx ; U
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pop edi ; V
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pop ebx ; U
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pop ebp ; V
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pop esi ; U
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ret ; NP
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_lbnMulN1_32 endp
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align 16
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_lbnMulAdd1_32 proc near
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push esi ; U
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mov esi,[esp+12] ; V load in
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push edi ; U
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mov edi,[esp+12] ; V load out
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push ebp ; U
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mov ebp,[esp+24] ; V load len
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push ebx ; U
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mov ecx,[esp+32] ; V load k
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;; First multiply step has no carry in.
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mov eax,[esi] ; U
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mov ebx,[edi] ; V
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mul ecx ; NP first multiply
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add ebx,eax ; U
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lea eax,[ebp*4-4] ; V loop unrolling
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adc edx,0 ; U
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and eax,12 ; V loop unrolling
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mov [edi],ebx ; U
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add esi,eax ; V loop unrolling
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add edi,eax ; U loop unrolling
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jmp DWORD PTR ma32_jumptable[eax] ; NP loop unrolling
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align 4
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ma32_jumptable:
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dd ma32_case0
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dd ma32_case1
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dd ma32_case2
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dd ma32_case3
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nop
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align 8
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nop
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nop
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nop ; To align loop properly
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ma32_case0:
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sub ebp,4 ; U
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jbe SHORT ma32_done ; V
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ma32_loop:
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mov eax,[esi+4] ; U
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mov ebx,edx ; V Remember carry for later
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add esi,16 ; U
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add edi,16 ; V
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mul ecx ; NP
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add eax,ebx ; U Add carry in from previous word
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mov ebx,[edi-12] ; V
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adc edx,0 ; U
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add ebx,eax ; V
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adc edx,0 ; U
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mov [edi-12],ebx ; V
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ma32_case3:
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mov eax,[esi-8] ; U
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mov ebx,edx ; V Remember carry for later
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mul ecx ; NP
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add eax,ebx ; U Add carry in from previous word
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mov ebx,[edi-8] ; V
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adc edx,0 ; U
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add ebx,eax ; V
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adc edx,0 ; U
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mov [edi-8],ebx ; V
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ma32_case2:
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mov eax,[esi-4] ; U
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mov ebx,edx ; V Remember carry for later
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mul ecx ; NP
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add eax,ebx ; U Add carry in from previous word
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mov ebx,[edi-4] ; V
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adc edx,0 ; U
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add ebx,eax ; V
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adc edx,0 ; U
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mov [edi-4],ebx ; V
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ma32_case1:
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mov eax,[esi] ; U
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mov ebx,edx ; V Remember carry for later
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mul ecx ; NP
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add eax,ebx ; U Add carry in from previous word
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mov ebx,[edi] ; V
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adc edx,0 ; U
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add ebx,eax ; V
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adc edx,0 ; U
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mov [edi],ebx ; V
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sub ebp,4 ; U
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ja SHORT ma32_loop ; V
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ma32_done:
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pop ebx ; U
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pop ebp ; V
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mov eax,edx ; U
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pop edi ; V
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pop esi ; U
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ret ; NP
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_lbnMulAdd1_32 endp
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align 16
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_lbnMulSub1_32 proc near
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push esi ; U
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mov esi,[esp+12] ; V load in
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push edi ; U
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mov edi,[esp+12] ; V load out
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push ebp ; U
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mov ebp,[esp+24] ; V load len
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push ebx ; U
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mov ecx,[esp+32] ; V load k
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;; First multiply step has no carry in.
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push esi ; U
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mov esi,[esp+12] ; V load in
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push edi ; U
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mov edi,[esp+12] ; V load out
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push ebp ; U
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mov ebp,[esp+24] ; V load len
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mov ecx,[esp+28] ; U load k
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;; First multiply step has no carry in.
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mov eax,[esi] ; V
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mov ebx,[edi] ; U
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mul ecx ; NP first multiply
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sub ebx,eax ; U
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lea eax,[ebp*4-4] ; V loop unrolling
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adc edx,0 ; U
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and eax,12 ; V loop unrolling
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mov [edi],ebx ; U
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add esi,eax ; V loop unrolling
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add edi,eax ; U loop unrolling
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jmp DWORD PTR ms32_jumptable[eax] ; NP loop unrolling
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align 4
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ms32_jumptable:
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dd ms32_case0
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dd ms32_case1
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dd ms32_case2
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dd ms32_case3
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nop
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align 8
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nop
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nop
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nop
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ms32_case0:
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sub ebp,4 ; U
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jbe SHORT ms32_done ; V
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ms32_loop:
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mov eax,[esi+4] ; U
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mov ebx,edx ; V Remember carry for later
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add esi,16 ; U
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add edi,16 ; V
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mul ecx ; NP
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add eax,ebx ; U Add carry in from previous word
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mov ebx,[edi-12] ; V
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adc edx,0 ; U
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sub ebx,eax ; V
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adc edx,0 ; U
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mov [edi-12],ebx ; V
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ms32_case3:
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mov eax,[esi-8] ; U
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mov ebx,edx ; V Remember carry for later
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mul ecx ; NP
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add eax,ebx ; U Add carry in from previous word
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mov ebx,[edi-8] ; V
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adc edx,0 ; U
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sub ebx,eax ; V
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adc edx,0 ; U
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mov [edi-8],ebx ; V
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ms32_case2:
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mov eax,[esi-4] ; U
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mov ebx,edx ; V Remember carry for later
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mul ecx ; NP
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add eax,ebx ; U Add carry in from previous word
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mov ebx,[edi-4] ; V
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adc edx,0 ; U
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sub ebx,eax ; V
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adc edx,0 ; U
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mov [edi-4],ebx ; V
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ms32_case1:
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mov eax,[esi] ; U
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mov ebx,edx ; V Remember carry for later
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mul ecx ; NP
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add eax,ebx ; U Add carry in from previous word
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mov ebx,[edi] ; V
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adc edx,0 ; U
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sub ebx,eax ; V
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adc edx,0 ; U
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mov [edi],ebx ; V
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sub ebp,4 ; U
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ja SHORT ms32_loop ; V
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ms32_done:
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pop ebx ; U
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pop ebp ; V
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mov eax,edx ; U
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pop edi ; V
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pop esi ; U
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ret ; NP
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_lbnMulSub1_32 endp
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;; Two-word by one-word divide. Stores quotient, returns remainder.
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;; BNWORD32 lbnDiv21_32(BNWORD32 *q, BNWORD32 nh, BNWORD32 nl, BNWORD32 d)
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;; 4 8 12 16
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align 4
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_lbnDiv21_32 proc near
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mov edx,[esp+8] ; U Load nh
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mov eax,[esp+12] ; V Load nl
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mov ecx,[esp+4] ; U Load q
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div DWORD PTR [esp+16] ; NP
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mov [ecx],eax ; U Store quotient
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mov eax,edx ; V Return remainder
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ret
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_lbnDiv21_32 endp
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;; Multi-word by one-word remainder.
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;; This speeds up key generation. It's not worth unrolling and so on;
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;; using 32-bit divides is enough of a speedup.
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;;
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;; The modulus (in ebp) is often 16 bits. Given that the dividend is 32
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;; bits, the chances of saving the first divide because the high word of the
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;; dividend is less than the modulus are low enough it's not worth taking
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;; the cycles to test for it.
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;;
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;; unsigned lbnModQ_32(BNWORD32 const *n, unsigned len, unsigned d)
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;; 4 8 12
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align 4
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_lbnModQ_32 proc near
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mov eax,[esp+4] ; U Load n
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push ebp ; V
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mov ebp,[esp+12] ; U Load len
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push esi ; V
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lea esi,[ebp*4+eax-4] ; U
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mov ecx,[esp+20] ; V Load d
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xor edx,edx ; U Clear edx for first iteration
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modq32_loop:
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mov eax,[esi] ; U Load new low word for divide
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sub esi,4 ; V
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div ecx ; NP edx = edx:eax % ecx
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dec ebp ; U
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jnz SHORT modq32_loop ; V
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pop esi ; U
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mov eax,edx ; V Return remainder in eax
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pop ebp ; U
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ret ; NP
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_lbnModQ_32 endp
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end
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